At-speed tests, which capture a test response at the rated clock speed, have become more and more important as integrated circuits' feature sizes continue to shrink and operating frequencies continue to increase. Functional tests may be used as at-speed tests, but they are expensive due to the cost of generating the tests and the cost of high speed functional testers. Thus, relatively inexpensive scan-based tests (scan tests) are widely adopted for at-speed testing digital integrated circuits (IC). While scan tests are less costly to implement with high fault coverage, they may violate various functional constraints on the circuit under test (CUT) and cause the CUT to operate in non-functional states during a test. Here, the terms of functional/non-functional states are used interchangeably with two other pairs of terms—legal/illegal and reachable/unreachable states—to denote the states of a circuit that can/cannot be reached during the functional operation of the circuit (i.e., the typical operation of the circuit while it is performing its intended functions). For example, for a BCD counter with four scan cells, only ten of the sixteen states are legal states. For more complex circuits, a much smaller percentage of their total possible states (i.e., both functional and nonfunctional states) are functional states.
Non-functional characteristics of test stimuli and test responses in scan tests may cause high switching activity at circuit nodes during a test. High switching activity may cause two problems. The first problem is overtesting. High switching activity requires high peak supply currents and thus results in high IR (product of current and resistance) drops. High IR drops may increase signal propagation delays that would not happen in a functional state of a CUT. As such, some good IC chips may fail at-speed tests, causing false yield losses. The second problem is high power dissipation. High switching activity may cause hot spots and permanent damage on a CUT. Therefore, it is important keep the switching activity of a CUT close to the switching activity that would be produced during its functional operation (i.e., the switching activity that would be produced by its functional states) to avoid overtesting and high power dissipation.
Several methods have been proposed to reduce overtesting and IR-drop during at-speed scan tests. One method, scan chain segmentation with gated clocking, divides scan chains into several segments and enables only one scan chain segment at a time to capture test responses. This reduces the number of gates affected by the state changes of scan cells and thus the switching activity in the circuit. However, this method not only increases test pattern counts, but consumes additional chip area and requires design effort to enable independently clocking scan segments.
Another method, functional scan testing, restricts the scan-in states to the set of reachable states to insure that the CUT operates only in the functional mode during capture cycles. Identifying reachable states, however, is highly complex for large designs. The pseudo-functional scan test method determines only a subset of illegal states and generates tests that avoid using any of the subset of illegal states as scan-in states. But even finding a set of illegal states sufficiently large may still be computationally intensive, especially in designs with multiple clock domains. Both functional and pseudo-functional scan test methods may also reduce fault coverage since they avoid detection of some faults that require non-functional scan-in states.
The method of partially-functional scan testing uses scan-in states that are at a minimal Hamming distance from a reachable state. By keeping the Hamming distance of scan-in states from reachable states to a small value, the switching activity caused by a test is close to or the same as that caused by reachable states.
In addition to the methods discussed above, various methods are based upon filling unspecified bits in test cubes. These methods, also known as “X-filling” methods because unspecified bits (i.e., “X-bits”) in a test cube are filled with some values, have a unique advantage over the above four methods. Specifically, X-filling may be used as a post-processing step in any conventional automated test pattern generation (ATPG) flow and thus requires no change to conventional ATPG procedures. The low-capture-power (LCP) X-filling method assigns 0s or 1s to the X-bits in a test cube to form a test pattern in a way such that the number of transitions at the outputs of scan cells is reduced in capture mode. While it is effective in reducing IR-drops, this method increases pattern counts significantly and is less scalable due to its long run time.
The preferred fill (PF) method has been discussed in S. Remersaro, et al, “Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs,” in Proc. of Intl. Test Conf., October 2006, pp. 1-10., which is incorporated herein by reference. The PF method attempts to reduce the Hamming distance between the initialized and captured patterns by using a procedure based on signal probabilities. This method does not need a long run time, but pattern counts are still significantly high.
The zero-fill method is also widely used, especially in test data compression procedures. This method increases the number of bits with a “0” value in a test vector, which helps reduce switching activity, especially during scan shift. Yet it also tends to increase pattern counts significantly.
While the X-filling methods reviewed above generate tests with low switching activity and power dissipation during testing, they may generate tests to detect a target fault that causes far less switching activity than in functional states, which may lead to undertesting.
A variety of hardware arrangements have been proposed to implement various scan test methods with controlled switching activity, including some of those discussed above, in EDT (embed deterministic test) environments. For example, low power test data encoding schemes adopt conventional LFSR (linear feedback shift register) reseeding techniques to reduce the scan-in transition probability. The method uses two LFSRs to produce test cubes and the corresponding mask bits. Outputs of both LFSRs are AND-ed or OR-ed to decrease the amount of switching. The use of extra seeds may compromise compression ratios, so some implementations of this method divide test cubes into blocks and only use reseeding to encode blocks that contain transitions. Other blocks are then replaced with a constant value, which is fed directly into scan chains.
The technique proposed in D. Czysz, et al., “Low Power Embedded Deterministic Test,” VLSI Test Symp., 9 pp. (May 6-10, 2007), which is incorporated herein by reference, identifies self-loop (SL) states of LFSRs to apply identical data to the scan chains for a number of shift cycles, thereby reducing the total number of transitions in scan cells. This technique tries to identify each slice of the test that has a specified bit a SL state. Then the remaining slices with no specified positions inherit SL states from their most adjacent neighbors. The result is a test vector in which many neighboring slices are identical. This reduces power consumed in the circuit during shift by reducing the number of transitions in the output of the scan cells.
In D. Czysz, et al., “Low Power Scan Shift and Capture in the EDT Environment,” Proceedings IEEE International Test Conference (ITC), paper 13.2, 2008, which is incorporated herein by reference, a technique is proposed to reduce power during both shift and capture periods in EDT based designs. It employs a controller that allows a given scan chain to be driven either by a power-aware EDT decompressor, or by a constant value fixed for the entire scan load. The same controller is used to decide which scan chains remain in a shift mode during the capture cycle by judiciously disabling scan clocks.